The present invention relates generally to voltage protection devices and particularly to transmission gate circuits used to selectively enable or disable a current path in electronic circuitry.
FIG. 1 is a block diagram of an integrated circuit 100 that includes a non-volatile flash memory 101 and other circuitry 102. The integrated circuit 100 also typically includes a number of pads for providing power supply voltages (e.g., VDD, VSS) to the integrated circuit and for conveying I/O signals between the integrated circuit 100 and external circuitry (not shown). In FIG. 1, just two pads 103 and 104 are shown as examples. An I/O (Input/Output) pad 103 can be used to provide both power to the flash memory 101 for programming or erasing flash memory cells and an I/O signal to the circuitry 102. The circuitry 102 typically includes MOS (metal oxide semiconductor) devices. An “I/O signal” can be an input signal, an output signal, or both an input signal and an output signal. “MPPAD” refers to a signal line 105 of the integrated circuit 100 that is connected between the I/O pad 103 and the circuitry 102 by way of transmission gate circuitry 106. In a flash characterization mode, when the I/O pad 103 receives a supply voltage for programming or erasing the flash memory 101, the I/O pad voltage may be set as high as 15 Volts, for example. For in/out and pull up/down paths of the circuitry 102, the maximum safe operating voltage is 3.6 Volts, in this example. For devices used in the transmission gate 106, the maximum safe operating voltage is 9 Volts, in this example. The level of I/O pad voltage could therefore damage the gate oxide and the source/drain junctions of the MOS devices of the circuitry 102 and the transmission gate circuitry 106 if no appropriate protection were provided. In the normal input/output mode of the integrated circuit 100 however, a low resistive path between the I/O pad 103 and the circuitry 102 is required. The transmission gate circuitry 106 and an associated voltage bias generation circuit 107 are provided between the I/O pad 103 and the circuitry 102 and arranged to isolate the circuitry 102 from the pad 103 to prevent damage when operating in flash characterization mode and to be conductive when the pad 103 is coupled to external circuitry to provide and receive an I/O signal.
FIG. 2 is a schematic circuit diagram of the transmission gate circuitry 106. The transmission gate circuitry 106 includes two serially connected transmission gates 201 and 203 that are connected between the MPPAD signal line 105 and the circuitry 102 of FIG. 1. The transmission gate circuitry 106 also includes a first PMOS control circuit 211 for controlling the conductivity of a first PMOS transistor 207 and a second PMOS control circuit 213 for controlling the conductivity of a second PMOS transistor 209. The transmission gate circuitry 106 also includes self-enabling circuitry 214 for enabling the first and second PMOS control circuits 211 and 213. The first PMOS control circuit 211 includes a PMOS transistor 215 having a body biased at VBIAS, a gate biased at VBIAS2, and a source coupled to the MPPAD signal line 105. The first PMOS control circuit 211 also includes an isolated NMOS transistor 217 having an N-Well biased at VBIAS, a drain connected to the gate of the first PMOS transistor 207 and the drain of the PMOS transistor 215, a body tied to its source, and a gate biased at VBIAS2. The first PMOS control circuit 211 also includes an NMOS transistor 219 having a body tied to its source, which is connected to VSS (ground), a drain connected to the source of the isolated NMOS transistor 217, and a gate controlled by an enable signal EN. The second PMOS control circuit 213 receives the enable signal EN and the bias signal VBIAS2. The transmission gate circuitry 106 acts to provide, in a first operating mode, a conductive path between the MPPAD signal line and a terminal (I/O SIGNAL) of the circuitry 102 and in a second operating mode, acts to isolate the circuitry 102 from the pad 103. The relative values of the MPPAD voltage, the bias voltages, VBIAS, VBIAS2 and supply voltage VDD and the state of the enable signal EN, determine the operating mode.
The transmission gate circuitry 106 does have some drawbacks, however. Many integrated circuit products require the transmission gate circuitry to support a true open drain mode of operation at the I/O pad, that is, receiving a relatively high input voltage of up to 5.5 Volts typically, while the I/O supply voltage VDD, is at a lower level, for example, between 1.7 Volts and 3.6 Volts. The transmission gate circuitry shown in FIG. 2 cannot support a true open drain mode of operation. This is because when the transmission gate circuitry 106 is in the first operating mode and providing a conductive path between the MPPAD signal line and the circuitry 102, with MPPAD at a higher voltage than VDD (open drain mode), the NMOS transistors 217 and 219 will try to pull the gate of the first PMOS transistor 207 to VSS (nominal ground) while the PMOS transistor 215 will try to pull the gate of the first PMOS transistor 207 to MPPAD (with the MPPAD voltage being higher than VBIAS2). This would cause signal contention issues and significant current being drawn from MPPAD.
Thus it would be advantageous to provide a transmission gate circuit that supports an open drain mode.